1. Field of the Invention
The present invention relates to technology for exchanging data between CPUs in a data processing apparatus having multiple CPUs.
2. Description of the Related Art
Data must be exchanged between CPUs in a data processing apparatus having multiple CPUs (referred to below as a multiprocessor data processing apparatus) in order to, for example, transfer command data or the data to be processed between the multiple CPUs.
Data is generally transferred over a bus. However, when multiple CPUs share a bus, transferring data between CPUs over the bus is inefficient because one CPU cannot access the bus when another CPU is using the bus, and the advantage of using multiple CPUs is thus lost. Registers, buffer memory, or similar means are therefore preferably used for data transfers in such cases. In this case, however, it is necessary to coordinate CPU operation in order to prevent different CPUs from writing data to the buffer at the same time, and to prevent one CPU from overwriting data in the buffer before another CPU has read the data, or before the other CPU writes data to the buffer. Multiple CPUs sharing a common buffer must therefore read and write data to the buffer using appropriate timing, and data transfers between CPUs sharing the buffer must be cooperatively controlled.
Control signals for adjusting this timing must therefore be exchanged between the multiple CPUs, and the CPU controller program must be written so that both CPUs input and output data using appropriate timing based on these control signals. The program thus becomes more complex due to the increased number of factors to be considered when writing the program. It may also be necessary for one CPU to wait for another CPU's process to end in order to prevent data loss when there are competing requests for data input/output (I/O), and the potential for a drop in processing speed is therefore great.